1. FIELD OF THE INVENTION
The present invention relates to a driving device and a liquid crystal display device which are suited for a simple matrix type liquid crystal display element to be driven by a driving method in which a plurality of lines are simultaneously selected.
2. DISCUSSION OF BACKGROUND
Conventionally, as driving methods for a simple matrix liquid crystal display device, there are a driving method based mainly on a so-called line successive driving system (a conventional Example 1) and a multiple line simultaneously selecting/driving method in which row electrodes are simultaneously selected or a multiple line addressing method (hereinbelow, referring to as a MLA driving method) (a conventional Example 2).
The conventional Example 1 is a driving method in which scanning voltages are successively applied to each row electrode, and at the same time, column voltages are applied to a plurality of column electrodes whereby brightness controlling voltages are applied to each of the row electrodes. Further, display dots are controlled to have transmittances in response to average effective voltages applied during a time in which the voltages are once applied to all the row electrodes (hereinbelow, referred to as a frame period). A predetermined picture image is displayed for each frame period.
The conventional Example 2 is a driving method as follows. All the row electrodes constituting a display surface area are divided into simultaneously selected groups each comprising a plurality of row electrodes, and scanning voltages are simultaneously applied to each of the row electrodes of the simultaneously selected groups. Further, column voltages are applied to a plurality of column electrodes at the same time of the application of the scanning voltages so that selection voltages are applied to a plurality of liquid crystal pixels to which the column voltages are simultaneously applied. The above-mentioned operation is repeated at least the same number of times as the simultaneously selected number of row electrodes.
As a result, the display dots are controlled to have transmittances in response to average effective voltages applied during a time in which the above-mentioned repeated operations complete (1 frame period), and a picture image is formed for each frame period.
In this conventional Example 2, the column voltages applied to column electrodes are voltages obtained by multiplying xe2x80x9ca unit column voltagexe2x80x9d with values determined by performing matrix operations of display data corresponding to a plurality of simultaneously selected row electrodes and a scanning voltage applied to the simultaneously selected row electrodes.
The maximum value of magnifying power obtained by the matrix operations suffers restriction by an orthogonal matrix for the scanning voltage used for the matrix operations. It takes at most a larger value between the number of rows or the number of columns in the matrix. As examples of the conventional Example 2, there are JP-A-6-27907, U.S. Pat. No. 5,262,881, JP-A-8-234164 and so on.
The above-mentioned liquid crystal display device has been used as a display device for a man-machine interface with the progress of highly intelligent society. In recent years, it is widely used not only for a desktop type personal computer but also for a notebook type personal computer, PDA (a portable information terminal) or a portable telephone, which is suitable for carrying, taking an advantage of thin and light in weight. As a result, in the development of the liquid crystal display device, improvement has been made to provide a large surface area, and on the other hand, improvements of reducing the weight and power consumption rate have been made.
In such liquid crystal display device, various measures have been taken to lower the power consumption rate. In more detail, there are measures to form a liquid crystal display element capable of responding to a low effective voltage, or to use a reflective type liquid crystal display element without requiring a backlight.
Further, as a conventional Example 3, there is a publication xe2x80x9cgeneral-purpose addressing technology for an effective value response type liquid crystal display device (a report of SID meeting 1988, p. 80-p.85)xe2x80x9d which reports the relation between the MLA driving method and consumption power. The conditions indicated by the conventional Example 3 are xe2x80x9cL={square root over (M)} (provided M represents the total number of row electrodes for a display picture surface and L represents a number of simultaneously selected rows)xe2x80x9d, and the optimum bias ratio at which a ratio of an effective voltage at an ON display time to an effective voltage at an OFF display time becomes the maximum (Bbest=maximum column voltage/scanning voltage=VC/VR). The publication reports that when the MLA driving was conducted under the above-mentioned conditions, a driving voltage for the liquid crystal display device can be reduced in comparison with that by a line successive driving method.
In JP-A-9-277650, when Lxe2x89xa0{square root over (M)} and the MLA driving is conducted under a condition other than using the optimum bias ratio, the ratio of an effective voltage at an ON display time to an effective voltage at an OFF display time does not show the maximum value. However, it is possible to set a supplied voltage to be lower. Further, in a case of producing a one-chip LSI capable of carrying out multiplex driving at a duty ratio of about {fraction (1/80)}, it was possible to integrate a driving circuit by a semiconductor manufacturing process for a 5-V standard logic IC. Further, capability of not only low consumption power but also reduction of manufacturing cost was shown (a conventional Example 4). On the other hand, for reducing power consumption rate by contriving a circuit structure, there is a method of lowering a clock frequency and conducting a parallel treatment.
Operations of the conventional Example 1 will be described with reference to FIGS. 7 and 11. FIG. 7 is a block diagram showing a controller-attached driving device 201 for driving a xe2x80x9c64 rowxc3x97132 columnxe2x80x9d-dot matrix type liquid crystal display element.
Interface signals I/F are inputted from an outer source to a controller 1. Row address signals ADRS and a read/write signal R/W are supplied from the controller 1 to a memory 2. Data DATA are supplied from an outer source to the memory 2.
RAMs for display data are built in the memory 2, and 1 dot in the built-in RAM corresponds to 1 dot in the liquid crystal panel in a one-to-one relation. The memory 2 decodes the row address signals ADRS from the controller 1 to output in parallel data (1 bit*132) for 1 row corresponding to the address signals, the outputted data being latched in line buffers 3 in synchronism with a clock.
A column voltage generating circuit 11 decodes display data (1 bit*132) from the line buffers 3 and a signal, for providing an alternate current to liquid crystal, i.e., a polarity inversion signal POL-CHG, supplied from the controller 1, and the decoded signals are supplied to a level shifter in which column voltages are suitably selected among levels of xe2x80x9cV0, V2, V3, V5xe2x80x9d. The selected column voltages are outputted to the liquid crystal panel 10 in synchronism with a clock CLK.
When rows are sequentially selected in a form of shift register in synchronism with the clock CLK, a row voltage generating circuit 9 decodes the polarity inversion signals POL-CHG and a value of register indicating selection or non-selection, and the decoded signals are supplied to a level shifter in which row voltages are formed suitably among xe2x80x9cV0, V1, V4, V5xe2x80x9d, the formed row voltages being outputted to the liquid crystal panel 10. In this case, when the row voltage generating circuit 9 selects then throw, synchronization is taken so that the column voltage generating circuit 11 outputs column voltages as data corresponding to the n th row in RAM.
Driving waveforms in a driving state are shown in FIG. 11. After a change of the polarity inversion signal POL-CHG (the Figure shows a state that there is a change from low to high), an alternate current which oscillates at both side with respect to the center of xe2x80x9cV2, V3xe2x80x9d levels is formed for each of a row output and a column output in synchronism with the clock CLK (a row waveform RW and a column waveform CW). Thus, under conditions of the multiplex driving and a low duty ratio, the method for treating in parallel all column signal data is used.
Operations of the conventional Example 2 will be described with reference to FIGS. 8 and 10. FIG. 8 is a block diagram of a controller-attached driving device 202 for a xe2x80x9c64 rowxc3x97132 columnxe2x80x9d-dot matrix type liquid crystal display element in which the number of simultaneously selected/driven rows is a and the number of imaginary rows is b. FIG. 10 shows an operational timing for each circuit.
In FIG. 8, the memory 2, in the same manner as in the line successive driving method, decodes row address signals ADRS from a controller 1 to output in parallel data for 1 row (1 bit*132), and outputted data are latched in a line buffer group 3 in synchronism with a clock CL1.
Values of address signals from the controller 1 are increased in synchronism with CL1. The same operations are repeated a times so that data for a rows are held in the line buffer group 3. D1, D2, . . . Da in FIG. 10 show data latched by line buffers 3 for each row of the first, the second, . . . the a throws respectively.
When data for a rows are stored, predetermined operations are conducted on the stored data and row selection pattern signals supplied from a row selection pattern generating circuit 7, and signals produced as a result of the operations are latched by a latch circuit 6 in synchronism with a clock CL2. A relation of timings of operation periods, latch data, clock CL1 and clock CL2 are shown in FIG. 10.
In FIG. 10, symbols CL1, CL2, LB1, LB2, LBa, RS, OT, LDATA, and R/C-Vout indicate respectively clock 1, clock 2, line buffer 1, line buffer 2, line buffer a, row selection signal, operation period, latch data and row/column voltage outputs.
As the row selection signal RS, 5 patterns of PAT-1 to PAT-5 are produced. The latch data LDATA hold a result of operations as OP-D1 to OP-D4 in order. Then, voltages are outputted to rows and columns (OUT1 to OUT3).
An operating circuit 52 shown in FIG. 8 executes, about data for a rows outputted from the line buffer group 3, imaginary data for b rows outputted from an imaginary data generating circuit 8 and a row selection pattern for (a+b) rows, an exclusive OR operation for each bit as shown in FIG. 6, to conduct operations to add (a+b) outputs.
In FIG. 6, there are inputs of a line buffer output LBout, a row selection pattern R-Spat and an imaginary data output P-Dout, and a result of operations is outputted to outputs 1 to a+b (out1 to outa+b). These operations are conducted in parallel to a 132 number of column signals. A result of operations outputted from the latch circuit 6 is supplied to a column voltage generating circuit 11. c-bit data supplied to the column voltage generating circuit 11 are passed through a decoder and a level shifter to be outputted as column voltages. In this case, for the c-bit data as a result of operations, there are considered (a+b+1) ways of 0, 1, 2 . . . (a+b) in outputted values when an adder circuit having (a+b) inputs is used, and the c-bit data correspond to those of outputted values.
However, the number of outputted values can be reduced when imaginary data are selected suitably. Hereinbelow, explanation will be made as to a method for adjusting bits in operations in a case of adding imaginary data and the imaginary data generating circuit 8 wherein 5 simultaneously selected rows and 3 imaginary rows are used.
FIG. 5 shows a xe2x80x9c8xc3x978, Hadamard""s matrix. 5 Bits in an upper place are for a matrix for rows to be actually selected and 3 bits in a lower place are for a matrix for imaginary rows. Here, a 5-row simultaneously selecting driving method without providing any imaginary row is considered. For example, in the data as shown in FIG. 12, when exclusive OR operations are executed for each bit in a xe2x80x9c5xc3x978xe2x80x9d matrix, values as a result of adding are xe2x80x9c0, 2, 2, 2, 1, 3, 3, 3xe2x80x9d for each column.
Further, in the data as shown in FIG. 13, values of xe2x80x9c4, 2, 2, 2, 5, 3, 3, 3xe2x80x9d are provided. In consideration of all other data, there are 6 ways of 0, 1, 2, 3, 4, 5xe2x80x9d as obtainable values. Namely, levels for column outputs are 6.
Assuming that xe2x80x9c1xe2x80x9d is at the 6 th row, xe2x80x9c0xe2x80x9d at the 7 th row, and xe2x80x9c0xe2x80x9d at the 8 th row in the data of FIG. 12, and the same operations as for the xe2x80x9c8xc3x978xe2x80x9d matrix in FIG. 5 are conducted. Then, outputs for each column are xe2x80x9c2, 4, 2, 4, 2, 4, 6, 4xe2x80x9d. Further, assuming that xe2x80x9c0xe2x80x9d at the 6 th row, xe2x80x9c0xe2x80x9d at the 7 th row and xe2x80x9c1xe2x80x9d at the 8 th row in the case of FIG. 13, and when the same operation as above-mentioned are conducted, outputted values are xe2x80x9c6, 4, 4, 2, 6, 4, 4, 6xe2x80x9d.
It is understood that when appropriate imaginary data are considered with respect to all 6-bit data, output values can be summarized to 3 ways of xe2x80x9c2, 4, 6xe2x80x9d. This can be considered as mentioned below.
As described above, output values in a case without providing any imaginary row are 6 ways of xe2x80x9c0, 1, 2, 3, 4, 5xe2x80x9d. However, output values can be changed in any value of xe2x80x9c0, +1, +2 or +3,xe2x80x9d when data for 3 rows as imaginary rows are provided. Accordingly, when an output value is 0 in a case without providing any imaginary row, it can be changed xe2x80x9c2xe2x80x9d. Similarly, it is possible to change an output value 1 to xe2x80x9c2xe2x80x9d or xe2x80x9c4xe2x80x9d, an output value of 2 to xe2x80x9c2xe2x80x9d or xe2x80x9c4xe2x80x9d, an output value of 3 to xe2x80x9c4xe2x80x9d or xe2x80x9c6xe2x80x9d, an output value of 4 to xe2x80x9c4xe2x80x9d or xe2x80x9c6xe2x80x9d and an output value of 5 to xe2x80x9c6xe2x80x9d. As a result, summarization to 3 ways of xe2x80x9c2, 4, 6xe2x80x9d can be made.
Based on these rules, the imaginary data generating circuit 8 can properly determine imaginary data with use of a a-bit decoder, a look-up table or the like. Thus, the effective bit number of outputs from the adder circuit 5 can be reduced with the data outputted from the imaginary data generating circuit 8. The row voltage generating circuit 9 decodes row selection signals outputted from the row selection signal generating circuit to apply row voltages to an a number of selected rows selected sequentially in a form of shift register. Output timings on row voltages and column voltages are shown in FIG. 10.
In the technique of the conventional Example 2, however, there were problems as follows because the driving device for determining imaginary rows to be driven comprised circuit blocks as described above.
Namely, when column signals were treated in parallel, a column voltage operating circuit, line buffers and an imaginary data generating circuit were required in comparison with the driving device of the conventional Example 1, for which the line successive driving method was used. Accordingly, the scale of circuit was increased and the surface area of a chip was increased. In an attempt to form the driving device in a form of a one-chip LSI, although a semiconductor manufacturing process for a 5-V standard logic IC could be utilized, cost for manufacturing was finally increased.
Further, when a clock speed was increased in order to suppress an increase of the circuit scale, a current to be consumed was increased. Thus, the circuit scale and the current to be consumed were in a relation of tradeoff. The present invention is to provide a driving device for a MLA driving method wherein the circuit structure is optimized and an increase of the circuit scale can be suppressed in a case of forming an integration circuit while an increase of a current to be consumed is minimized.
In accordance with an embodiment 1 of the present invention, there is provided a driving device comprising an imaginary data generating means, a row electrode driving means, a column electrode driving means, a memory means for memorizing display data, an operating means for operating column output voltages and a row selection pattern generating means for outputting a row selection pattern wherein a kxc2x7m number (k is an integer of not less than 2 and m is an integer of not less than 1) of simultaneously selected/driven rows and a kxc2x7n number (n is an integer of not less than 1) of imaginary row are determined for a liquid crystal display element comprising row electrodes and column electrodes arranged in a matrix form and the display element is driven by a MLA driving method, the driving device being characterized in that a matrix B is used for a row selection pattern, which is formed by expanding a matrix A of (m+n) rows where row vectors perpendicularly intersect each other, and column output voltages are operated with a unit of A.
Further, according to an embodiment 2, there is provided a driving device comprising a row electrode driving means, a column electrode driving means, a memory means for memorizing display data, an operating means for operating column output voltages and a row selection pattern generating means for outputting a row selection pattern wherein a kxc2x7m number (k is an integer of not less than 2 and m is an integer of not less than 1) of simultaneously selected/driven rows and k rows of imaginary row are determined for a liquid crystal display element comprising row electrodes and column electrodes arranged in a matrix form and the display element is driven by a MLA driving method, the driving device being characterized in that a matrix B is used for a row selection pattern, which is formed by expanding a matrix A of (m rows+1 imaginary row) where row vectors perpendicularly intersect each other, and column output voltages are operated with a unit of A.
Further, as an embodiment 3, there is provided the driving device according to the embodiment 1 or the embodiment 2, wherein the matrix B in which row vectors perpendicularly intersect each other is used, provided that in the below-mentioned formula (1), P1, P2, P3 and p4 are respectively 1 or xe2x88x921, and P1xc2x7P2xc2x7P3xc2x7P4=xe2x88x921:                     B        =                              [                                                                                                      p                      1                                        ·                    A                                                                                                              p                      2                                        ·                    A                                                                                                                                          p                      3                                        ·                    A                                                                                                              p                      4                                        ·                    A                                                                        ]                    .                                    (        1        )            
Further, according to an embodiment 4, there is provided the driving device according to the embodiment 3, wherein a matrix C in which row vectors perpendicularly intersect each other is used, provided that in the below-mentioned formula (2), P5, P6, P7 and P8 are respectively 1 or xe2x88x921, and P5xc2x7P6xc2x7P7xc2x7P8=xe2x88x921:                     C        =                              [                                                                                                      p                      5                                        ·                    B                                                                                                              p                      6                                        ·                    B                                                                                                                                          p                      7                                        ·                    B                                                                                                              p                      8                                        ·                    B                                                                        ]                    .                                    (        2        )            
Further, there is provided the above-mentioned driving devices, wherein the rows and/or the columns in the matrix B or the matrix C are exchanged. Further, there is provided the above-mentioned driving devices wherein signs on columns in the matrix B or the matrix C are reversed. Further, there is provided the above-mentioned driving devices wherein k=2 and m=3. Further, there is provided the above-mentioned driving devices wherein K=2, m=3 and n=1.
Further, as an embodiment 5, there is provided the driving device as described in the embodiment 1, 2, 3 or 4 wherein the device is in a one-chip LSI. In this case, it is preferable that an oscillating circuit and a power source circuit are built in.
Further, as an embodiment 6, there is provided a liquid crystal display device provided with the driving device as described in the embodiment 1, 2, 3, 4 or 5 and liquid crystal display element.